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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vts/HatayamaHMY97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hiromichi_Yamada>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kazumi_Hatayama>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kazunori_Hikone>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Takeshi_Miyazaki>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVTEST.1997.599436>
foaf:homepage <https://doi.org/10.1109/VTEST.1997.599436>
dc:identifier DBLP conf/vts/HatayamaHMY97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVTEST.1997.599436 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label A practical approach to instruction-based test generation for functional modules of VLSI processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hiromichi_Yamada>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kazumi_Hatayama>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kazunori_Hikone>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Takeshi_Miyazaki>
swrc:pages 17-23 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vts/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vts/HatayamaHMY97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vts/HatayamaHMY97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vts/vts1997.html#HatayamaHMY97>
rdfs:seeAlso <https://doi.org/10.1109/VTEST.1997.599436>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vts>
dc:subject VLSI; VLSI processors; functional modules; instruction-based test generation; functional test pattern generation; gate level faults; constrained test generation; ALPS; ALU oriented test pattern generation system (xsd:string)
dc:title A practical approach to instruction-based test generation for functional modules of VLSI processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document