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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vts/HuangCC97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kuang-Chien_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kwang-Ting_Cheng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shi-Yu_Huang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVTEST.1997.599466>
foaf:homepage <https://doi.org/10.1109/VTEST.1997.599466>
dc:identifier DBLP conf/vts/HuangCC97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVTEST.1997.599466 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label Incremental logic rectification. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kuang-Chien_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kwang-Ting_Cheng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shi-Yu_Huang>
swrc:pages 143-149 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vts/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vts/HuangCC97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vts/HuangCC97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vts/vts1997.html#HuangCC97>
rdfs:seeAlso <https://doi.org/10.1109/VTEST.1997.599466>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vts>
dc:subject logic CAD; incremental logic rectification; incorrect combinational circuit; symbolic BDD techniques; sequence of partial corrections; circuits with multiple errors; general single-gate correction; hybrid approach; structural correspondence; specification; implementation; ISCAS85 benchmark circuits; VLSI design; error region pruning (xsd:string)
dc:title Incremental logic rectification. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document