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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vts/HuangL96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fabrizio_Lombardi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei-Kang_Huang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVTEST.1996.510892>
foaf:homepage <https://doi.org/10.1109/VTEST.1996.510892>
dc:identifier DBLP conf/vts/HuangL96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVTEST.1996.510892 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label An approach for testing programmable/configurable field programmable gate arrays. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fabrizio_Lombardi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei-Kang_Huang>
swrc:pages 450-455 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vts/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vts/HuangL96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vts/HuangL96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vts/vts1996.html#HuangL96>
rdfs:seeAlso <https://doi.org/10.1109/VTEST.1996.510892>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vts>
dc:subject field programmable gate arrays; logic testing; integrated circuit testing; VLSI; FPGA testing; field programmable gate arrays; hybrid fault model; behavioral characterization; single fault detection; stuck-at fault; functional fault; disjoint one-dimensional arrays; unilateral horizontal connections; common vertical input lines; array testing; logic blocks (xsd:string)
dc:title An approach for testing programmable/configurable field programmable gate arrays. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document