A methodolgy for characterizing cell testability.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vts/JeeF97
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1997
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A methodolgy for characterizing cell testability.
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integrated circuit design; cell testability; integrated circuit design; stuck-at fault coverage; IC quality; DPM; manufacturing defects; metric; physical design for testability
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A methodolgy for characterizing cell testability.
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