Critical hazard free test generation for asynchronous circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vts/KhocheB97
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1997
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Critical hazard free test generation for asynchronous circuits.
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asynchronous circuits; self-timed control circuits; asynchronous circuits; critical hazard-free tests; six-valued algebra; macro-module library; partial scan based DFT environment; unbounded delay model; D-algorithm
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Critical hazard free test generation for asynchronous circuits.
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