Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vts/LeeHRP96
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Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.
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CMOS digital integrated circuits; VLSI; automatic testing; genetic algorithms; integrated circuit testing; fault location; logic testing; GA-based test generators; ATPG; bridging faults; CMOS VLSI circuits; automatic test pattern generator; I/sub DDQ/ current testing; CMOS digital circuits; two-line bridging fault set; adaptive genetic algorithm; compact test set generation
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Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.
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