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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vts/LiLQSW03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/D._M._H._Walker>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wangqi_Qiu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Weiping_Shi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiang_Lu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhuo_Li_0001>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVTEST.2003.1197678>
foaf:homepage <https://doi.org/10.1109/VTEST.2003.1197678>
dc:identifier DBLP conf/vts/LiLQSW03 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVTEST.2003.1197678 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
rdfs:label A Circuit Level Fault Model for Resistive Opens and Bridges. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/D._M._H._Walker>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wangqi_Qiu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Weiping_Shi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiang_Lu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhuo_Li_0001>
swrc:pages 379-384 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vts/2003>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vts/LiLQSW03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vts/LiLQSW03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vts/vts2003.html#LiLQSW03>
rdfs:seeAlso <https://doi.org/10.1109/VTEST.2003.1197678>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vts>
dc:title A Circuit Level Fault Model for Resistive Opens and Bridges. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document