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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vts/LiaoW96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/D._M._H._Walker>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yuyun_Liao>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVTEST.1996.510878>
foaf:homepage <https://doi.org/10.1109/VTEST.1996.510878>
dc:identifier DBLP conf/vts/LiaoW96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVTEST.1996.510878 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Optimal voltage testing for physically-based faults. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/D._M._H._Walker>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yuyun_Liao>
swrc:pages 344-353 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vts/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vts/LiaoW96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vts/LiaoW96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vts/vts1996.html#LiaoW96>
rdfs:seeAlso <https://doi.org/10.1109/VTEST.1996.510878>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vts>
dc:subject integrated circuit testing; CMOS logic circuits; fault diagnosis; logic testing; logic gates; delays; integrated circuit noise; automatic testing; optimal voltage testing; physically-based faults; CMOS circuits; resistive bridges; gate outputs; pattern sensitive functional faults; transmission gates; delay faults; test vector; fault coverage; selection strategy; noise margin; low-voltage testing; Iddq tests (xsd:string)
dc:title Optimal voltage testing for physically-based faults. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document