Switch-level modeling of transistor-level stuck-at faults.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vts/LidenD95
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1995
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Switch-level modeling of transistor-level stuck-at faults.
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CMOS logic circuits; fault diagnosis; logic testing; integrated circuit modelling; integrated circuit testing; circuit analysis computing; switch-level modeling; transistor-level stuck-at faults; switch-level algorithms; fault modeling capability; fault detection measures; confidence degradation; unknown output values; uncertainty quantification; node model; CMOS circuits
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Switch-level modeling of transistor-level stuck-at faults.
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