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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vts/LidenD95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peter_Dahlgren>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peter_Lid%E2%88%9A%C2%A9n>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVTEST.1995.512639>
foaf:homepage <https://doi.org/10.1109/VTEST.1995.512639>
dc:identifier DBLP conf/vts/LidenD95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVTEST.1995.512639 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Switch-level modeling of transistor-level stuck-at faults. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peter_Dahlgren>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peter_Lid%E2%88%9A%C2%A9n>
swrc:pages 208-215 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vts/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vts/LidenD95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vts/LidenD95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vts/vts1995.html#LidenD95>
rdfs:seeAlso <https://doi.org/10.1109/VTEST.1995.512639>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vts>
dc:subject CMOS logic circuits; fault diagnosis; logic testing; integrated circuit modelling; integrated circuit testing; circuit analysis computing; switch-level modeling; transistor-level stuck-at faults; switch-level algorithms; fault modeling capability; fault detection measures; confidence degradation; unknown output values; uncertainty quantification; node model; CMOS circuits (xsd:string)
dc:title Switch-level modeling of transistor-level stuck-at faults. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document