Checking experiments to test latches.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vts/MakarM95
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1995
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Checking experiments to test latches.
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CMOS logic circuits; logic testing; sequential circuits; fault diagnosis; circuit analysis computing; SPICE; finite state machines; integrated circuit testing; exhaustive functional tests; checking experiments; 2-state latches; minimum-length checking; D-latch; simulation; HSpice implementation; transmission gate latch; detectable shorted interconnects; open interconnects; short-to-power faults; short-to-ground faults; stuck open faults; stuck-on faults; pin fault test set; multiplexer-based test set; sequential elements; 2-state state machines; CMOS
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Checking experiments to test latches.
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