An apparatus for pseudo-deterministic testing.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vts/MukundMR95
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1995
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An apparatus for pseudo-deterministic testing.
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logic testing; built-in self test; shift registers; integrated circuit testing; pseudo-deterministic testing; deterministic patterns; pseudo-random sequences; at-speed BIST; arbitrary length shift register; LFSR; care bits; test vector; tap configurations; test segments; don't care bits; random pattern resistant faults; interconnected logic blocks; computational efficiency
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An apparatus for pseudo-deterministic testing.
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