Consistently dominant fault model for tristate buffer nets.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vts/Powell96
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Consistently dominant fault model for tristate buffer nets.
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fault diagnosis; logic testing; integrated logic circuits; integrated circuit testing; VLSI; fault location; buffer circuits; ternary logic; multivalued logic circuits; consistently dominant fault model; tristate buffer nets; floating type faults; contention type faults; MISR signature loss; test pattern compression; fault detection; stuck faults
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Consistently dominant fault model for tristate buffer nets.
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