Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming .
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vts/ShaikB95
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1995
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Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming .
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built-in self test; delays; automatic testing; integrated circuit testing; hazards and race conditions; quadratic programming; VLSI; integrated circuit design; logic design; logic testing; digital integrated circuits; circuit design; low overhead delay-fault BIST; constrained quadratic 0-1 programming; built-in self testing model; weighted signed graph balancing problem
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Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming .
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