Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vts/TsengHL10
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Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost.
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Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost.
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