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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vts/WendlingRL96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/R%E2%88%9A%C2%A9gis_Leveugle>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rapha%E2%88%9A%C4%99l_Rochet>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/X._Wendling>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVTEST.1996.510839>
foaf:homepage <https://doi.org/10.1109/VTEST.1996.510839>
dc:identifier DBLP conf/vts/WendlingRL96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVTEST.1996.510839 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Standard and ROM-based synthesis of FSMs with control flow checking capabilities. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/R%E2%88%9A%C2%A9gis_Leveugle>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rapha%E2%88%9A%C4%99l_Rochet>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/X._Wendling>
swrc:pages 81-86 (xsd:string)
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owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vts/WendlingRL96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vts/WendlingRL96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vts/vts1996.html#WendlingRL96>
rdfs:seeAlso <https://doi.org/10.1109/VTEST.1996.510839>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vts>
dc:subject finite state machines; integrated circuit design; integrated circuit testing; read-only storage; error detection; automatic testing; FSM; control flow checking; sequencing error detection; finite state machine; automatic synthesis; ROM architecture (xsd:string)
dc:title Standard and ROM-based synthesis of FSMs with control flow checking capabilities. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document