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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vts/WuHCW00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cheng-Wen_Wu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chi-Feng_Wu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chih-Tsun_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kuo-Liang_Cheng>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVTEST.2000.843857>
foaf:homepage <https://doi.org/10.1109/VTEST.2000.843857>
dc:identifier DBLP conf/vts/WuHCW00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVTEST.2000.843857 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label Simulation-Based Test Algorithm Generation for Random Access Memories. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cheng-Wen_Wu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chi-Feng_Wu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chih-Tsun_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kuo-Liang_Cheng>
swrc:pages 291-296 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vts/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vts/WuHCW00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vts/WuHCW00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vts/vts2000.html#WuHCW00>
rdfs:seeAlso <https://doi.org/10.1109/VTEST.2000.843857>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vts>
dc:subject RAM testing, RAM fault simulation, March test algorithm, semiconductor memories, Cocktail-March test algorithms (xsd:string)
dc:title Simulation-Based Test Algorithm Generation for Random Access Memories. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document