An on-line testable UART implemented using IFIS.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vts/YeandelTJ97
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1997
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An on-line testable UART implemented using IFIS.
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data communication equipment; online testable UART; IFIS methodology; complex integrated circuit; FPGA technology; dual-rail coding; handshaking protocol; failure detection
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An on-line testable UART implemented using IFIS.
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