Resynthesis for sequential circuits designed with a specified initial state.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vts/YotsuyanagiKK95
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1995
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Resynthesis for sequential circuits designed with a specified initial state.
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sequential circuits; logic CAD; circuit optimisation; timing; redundancy; flip-flops; synchronous sequential circuits; specified initial state; retiming method; redundancy removal method; resynthesized circuit; input sequences; flip-flops; logic optimisation
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Resynthesis for sequential circuits designed with a specified initial state.
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