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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vts/YotsuyanagiKK95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hiroyuki_Yotsuyanagi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kozo_Kinoshita>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Seiji_Kajihara>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVTEST.1995.512630>
foaf:homepage <https://doi.org/10.1109/VTEST.1995.512630>
dc:identifier DBLP conf/vts/YotsuyanagiKK95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVTEST.1995.512630 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Resynthesis for sequential circuits designed with a specified initial state. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hiroyuki_Yotsuyanagi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kozo_Kinoshita>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Seiji_Kajihara>
swrc:pages 152-157 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vts/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vts/YotsuyanagiKK95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vts/YotsuyanagiKK95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vts/vts1995.html#YotsuyanagiKK95>
rdfs:seeAlso <https://doi.org/10.1109/VTEST.1995.512630>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vts>
dc:subject sequential circuits; logic CAD; circuit optimisation; timing; redundancy; flip-flops; synchronous sequential circuits; specified initial state; retiming method; redundancy removal method; resynthesized circuit; input sequences; flip-flops; logic optimisation (xsd:string)
dc:title Resynthesis for sequential circuits designed with a specified initial state. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document