Scalable cache memory design for large-scale SMT architectures. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Muhamed_F._Mudawar>
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dc:identifier	DBLP conf/wmpi/Mudawar04 (xsd:string)
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dcterms:issued	2004 (xsd:gYear)
rdfs:label	Scalable cache memory design for large-scale SMT architectures. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Muhamed_F._Mudawar>
swrc:pages	65-71 (xsd:string)
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/wmpi/wmpi2004.html#Mudawar04>
rdfs:seeAlso	<https://doi.org/10.1145/1054943.1054952>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/wmpi>
dc:subject	scalable multiported cache memory, simultaneous multithreaded architectures (xsd:string)
dc:title	Scalable cache memory design for large-scale SMT architectures. (xsd:string)
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