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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/wosp/VeltenSIH22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Daniel_Hackenberg>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Markus_Velten>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Robert_Sch%E2%88%9A%E2%88%82ne>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Thomas_Ilsche>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3489525.3511689>
foaf:homepage <https://doi.org/10.1145/3489525.3511689>
dc:identifier DBLP conf/wosp/VeltenSIH22 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3489525.3511689 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label Memory Performance of AMD EPYC Rome and Intel Cascade Lake SP Server Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Daniel_Hackenberg>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Markus_Velten>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Robert_Sch%E2%88%9A%E2%88%82ne>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Thomas_Ilsche>
swrc:pages 165-175 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/wosp/2022>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/wosp/VeltenSIH22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/wosp/VeltenSIH22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/wosp/icpe2022.html#VeltenSIH22>
rdfs:seeAlso <https://doi.org/10.1145/3489525.3511689>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/wosp>
dc:title Memory Performance of AMD EPYC Rome and Intel Cascade Lake SP Server Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document