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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/access/BarlaJB20>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Prashanth_Barla>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Somashekara_Bhat>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vinod_Kumar_Joshi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FACCESS.2019.2963727>
foaf:homepage <https://doi.org/10.1109/ACCESS.2019.2963727>
dc:identifier DBLP journals/access/BarlaJB20 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FACCESS.2019.2963727 (xsd:string)
dcterms:issued 2020 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/access>
rdfs:label A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Prashanth_Barla>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Somashekara_Bhat>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vinod_Kumar_Joshi>
swrc:pages 6876-6889 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/access/BarlaJB20/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/access/BarlaJB20>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/access/access8.html#BarlaJB20>
rdfs:seeAlso <https://doi.org/10.1109/ACCESS.2019.2963727>
dc:title A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 8 (xsd:string)