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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/access/ZaganG23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ionel_Zagan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vasile_Gheorghita_Gaitan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FACCESS.2023.3266150>
foaf:homepage <https://doi.org/10.1109/ACCESS.2023.3266150>
dc:identifier DBLP journals/access/ZaganG23 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FACCESS.2023.3266150 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/access>
rdfs:label Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ionel_Zagan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vasile_Gheorghita_Gaitan>
swrc:pages 36264-36280 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/access/ZaganG23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/access/ZaganG23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/access/access11.html#ZaganG23>
rdfs:seeAlso <https://doi.org/10.1109/ACCESS.2023.3266150>
dc:title Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 11 (xsd:string)