VLSI Circuit Performance Optimization by Geometric Programming.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/anor/ChuW01
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dcterms:
bibliographicCitation
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http://dblp.uni-trier.de/rec/bibtex/journals/anor/ChuW01
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Chris_C._N._Chu
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/D._F._Wong_0001
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http://dx.doi.org/doi.org%2F10.1023%2FA%3A1013345330079
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DBLP journals/anor/ChuW01
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DOI doi.org%2F10.1023%2FA%3A1013345330079
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issued
2001
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VLSI Circuit Performance Optimization by Geometric Programming.
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https://dblp.l3s.de/d2r/resource/authors/Chris_C._N._Chu
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https://dblp.l3s.de/d2r/resource/authors/D._F._Wong_0001
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swrc:
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1-4
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swrc:
pages
37-60
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rdfs:
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seeAlso
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dc:
subject
VLSI design; unary geometric programming; circuit performance optimization; transistor sizing; gate sizing; wire sizing; Lagrangian relaxation
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dc:
title
VLSI Circuit Performance Optimization by Geometric Programming.
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105
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