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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/cee/WiersemaBP16>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arne_Bockhorn>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marco_Platzner>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tobias_Wiersema>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1016%2Fj.compeleceng.2016.04.005>
foaf:homepage <https://doi.org/10.1016/j.compeleceng.2016.04.005>
dc:identifier DBLP journals/cee/WiersemaBP16 (xsd:string)
dc:identifier DOI doi.org%2F10.1016%2Fj.compeleceng.2016.04.005 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/cee>
rdfs:label An architecture and design tool flow for embedding a virtual FPGA into a reconfigurable system-on-chip. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arne_Bockhorn>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marco_Platzner>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tobias_Wiersema>
swrc:pages 112-122 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/cee/WiersemaBP16/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/cee/WiersemaBP16>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/cee/cee55.html#WiersemaBP16>
rdfs:seeAlso <https://doi.org/10.1016/j.compeleceng.2016.04.005>
dc:title An architecture and design tool flow for embedding a virtual FPGA into a reconfigurable system-on-chip. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 55 (xsd:string)