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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/cit/Roy07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kuntal_Roy>
foaf:homepage <http://dx.doi.org/doi.org%2F10.2498%2Fcit.1000731>
foaf:homepage <https://doi.org/10.2498/cit.1000731>
dc:identifier DBLP journals/cit/Roy07 (xsd:string)
dc:identifier DOI doi.org%2F10.2498%2Fcit.1000731 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/cit>
rdfs:label Optimum Gate Ordering of CMOS Logic Gates using Euler Path Approach: Some Insights and Explanations. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kuntal_Roy>
swrc:number 1 (xsd:string)
swrc:pages 85-92 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/cit/Roy07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/cit/Roy07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/cit/cit15.html#Roy07>
rdfs:seeAlso <https://doi.org/10.2498/cit.1000731>
dc:title Optimum Gate Ordering of CMOS Logic Gates using Euler Path Approach: Some Insights and Explanations. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 15 (xsd:string)