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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/cj/BousiasHJ06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chris_R._Jesshope>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kostas_Bousias>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nabil_Hasasneh>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1093%2Fcomjnl%2Fbxh157>
foaf:homepage <https://doi.org/10.1093/comjnl/bxh157>
dc:identifier DBLP journals/cj/BousiasHJ06 (xsd:string)
dc:identifier DOI doi.org%2F10.1093%2Fcomjnl%2Fbxh157 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/cj>
rdfs:label Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chris_R._Jesshope>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kostas_Bousias>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nabil_Hasasneh>
swrc:number 2 (xsd:string)
swrc:pages 211-233 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/cj/BousiasHJ06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/cj/BousiasHJ06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/cj/cj49.html#BousiasHJ06>
rdfs:seeAlso <https://doi.org/10.1093/comjnl/bxh157>
dc:title Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 49 (xsd:string)