Design and analysis of per-flow queueing switches and VC-merge switches based on per-VC queueing architecture.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/comcom/ZhouY00
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Design and analysis of per-flow queueing switches and VC-merge switches based on per-VC queueing architecture.
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Design and analysis of per-flow queueing switches and VC-merge switches based on per-VC queueing architecture.
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