Perimeter Degree Technique for the Reduction of Routing Congestion during Placement in Physical Design of VLSI Circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/complexity/LakshmannaSGSKS22
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Perimeter Degree Technique for the Reduction of Routing Congestion during Placement in Physical Design of VLSI Circuits.
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Perimeter Degree Technique for the Reduction of Routing Congestion during Placement in Physical Design of VLSI Circuits.
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