Analysis and Design of a 32nm FinFET Dynamic Latch Comparator. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Mir_Muntasir_Hossain>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Satyendra_N._Biswas>
foaf:homepage	<http://arxiv.org/abs/1910.00098>
dc:identifier	DBLP journals/corr/abs-1910-00098 (xsd:string)
dcterms:issued	2019 (xsd:gYear)
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rdfs:label	Analysis and Design of a 32nm FinFET Dynamic Latch Comparator. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Mir_Muntasir_Hossain>
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dc:title	Analysis and Design of a 32nm FinFET Dynamic Latch Comparator. (xsd:string)
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