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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/corr/abs-2310-18384>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michael_Beigl>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tobias_King>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tobias_R%E2%88%9A%E2%88%82ddiger>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yexu_Zhou>
foaf:homepage <http://dx.doi.org/doi.org%2F10.48550%2FarXiv.2310.18384>
foaf:homepage <https://doi.org/10.48550/arXiv.2310.18384>
dc:identifier DBLP journals/corr/abs-2310-18384 (xsd:string)
dc:identifier DOI doi.org%2F10.48550%2FarXiv.2310.18384 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/corr>
rdfs:label MicroNAS: Memory and Latency Constrained Hardware-Aware Neural Architecture Search for Time Series Classification on Microcontrollers. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michael_Beigl>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tobias_King>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tobias_R%E2%88%9A%E2%88%82ddiger>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yexu_Zhou>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/corr/abs-2310-18384/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/corr/abs-2310-18384>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/corr/corr2310.html#abs-2310-18384>
rdfs:seeAlso <https://doi.org/10.48550/arXiv.2310.18384>
dc:title MicroNAS: Memory and Latency Constrained Hardware-Aware Neural Architecture Search for Time Series Classification on Microcontrollers. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume abs/2310.18384 (xsd:string)