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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/cssp/SahaniSA22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alpana_Agarwal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anil_Singh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jagdeep_Kaur_Sahani>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs00034-021-01861-z>
foaf:homepage <https://doi.org/10.1007/s00034-021-01861-z>
dc:identifier DBLP journals/cssp/SahaniSA22 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs00034-021-01861-z (xsd:string)
dcterms:issued 2022 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/cssp>
rdfs:label A 1 őľs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alpana_Agarwal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anil_Singh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jagdeep_Kaur_Sahani>
swrc:number 3 (xsd:string)
swrc:pages 1299-1323 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/cssp/SahaniSA22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/cssp/SahaniSA22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/cssp/cssp41.html#SahaniSA22>
rdfs:seeAlso <https://doi.org/10.1007/s00034-021-01861-z>
dc:title A 1 őľs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 41 (xsd:string)