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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/dafes/LeiteW16>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marcela_Leite>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marco_Aur%E2%88%9A%C2%A9lio_Wehrmeister>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs10617-016-9172-6>
foaf:homepage <https://doi.org/10.1007/s10617-016-9172-6>
dc:identifier DBLP journals/dafes/LeiteW16 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs10617-016-9172-6 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/dafes>
rdfs:label System-level design based on UML/MARTE for FPGA-based embedded real-time systems. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marcela_Leite>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marco_Aur%E2%88%9A%C2%A9lio_Wehrmeister>
swrc:number 2 (xsd:string)
swrc:pages 127-153 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/dafes/LeiteW16/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/dafes/LeiteW16>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/dafes/dafes20.html#LeiteW16>
rdfs:seeAlso <https://doi.org/10.1007/s10617-016-9172-6>
dc:title System-level design based on UML/MARTE for FPGA-based embedded real-time systems. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 20 (xsd:string)