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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/dt/Fetzer06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Eric_S._Fetzer>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FMDT.2006.159>
foaf:homepage <https://doi.org/10.1109/MDT.2006.159>
dc:identifier DBLP journals/dt/Fetzer06 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FMDT.2006.159 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/dt>
rdfs:label Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Eric_S._Fetzer>
swrc:number 6 (xsd:string)
swrc:pages 476-483 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/dt/Fetzer06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/dt/Fetzer06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/dt/dt23.html#Fetzer06>
rdfs:seeAlso <https://doi.org/10.1109/MDT.2006.159>
dc:subject dual core, Itanium microprocessor, Montecito, adaptive circuits, process variation, power measurement, cache safe technology, active clock deskew (xsd:string)
dc:title Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 23 (xsd:string)