A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/dt/HanLLL19
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2019
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A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties.
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A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties.
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