Yield-Driven, False-Path-Aware Clock Skew Scheduling.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/dt/TsaiBCS05
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2005
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Yield-Driven, False-Path-Aware Clock Skew Scheduling.
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214-222
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dc:
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clock skew scheduling, performance-related circuit yield loss, circuit-level parameters, DFM
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Yield-Driven, False-Path-Aware Clock Skew Scheduling.
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