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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/dt/XingY98>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shanzhen_Xing>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/William_W._H._Yu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F54.655179>
foaf:homepage <https://doi.org/10.1109/54.655179>
dc:identifier DBLP journals/dt/XingY98 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F54.655179 (xsd:string)
dcterms:issued 1998 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/dt>
rdfs:label FPGA Adders: Performance Evaluation and Optimal Design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shanzhen_Xing>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/William_W._H._Yu>
swrc:number 1 (xsd:string)
swrc:pages 24-29 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/dt/XingY98/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/dt/XingY98>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/dt/dt15.html#XingY98>
rdfs:seeAlso <https://doi.org/10.1109/54.655179>
dc:title FPGA Adders: Performance Evaluation and Optimal Design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 15 (xsd:string)