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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/dt/ZengLRG05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Annie_%28Yujuan%29_Zeng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/James_%28JianQiang%29_L%E2%88%9A%C4%BE>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kenneth_Rose>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ronald_J._Gutmann>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FMDT.2005.138>
foaf:homepage <https://doi.org/10.1109/MDT.2005.138>
dc:identifier DBLP journals/dt/ZengLRG05 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FMDT.2005.138 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/dt>
rdfs:label First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Annie_%28Yujuan%29_Zeng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/James_%28JianQiang%29_L%E2%88%9A%C4%BE>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kenneth_Rose>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ronald_J._Gutmann>
swrc:number 6 (xsd:string)
swrc:pages 548-555 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/dt/ZengLRG05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/dt/ZengLRG05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/dt/dt22.html#ZengLRG05>
rdfs:seeAlso <https://doi.org/10.1109/MDT.2005.138>
dc:subject Access time, cycle time, cache performance, wafer-level 3D integration, SRAM, DRAM (xsd:string)
dc:title First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 22 (xsd:string)