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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/esl/YangMSP14>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dhiraj_K._Pradhan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jimson_Mathew>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rishad_A._Shafik>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yuanfan_Yang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FLES.2013.2278740>
foaf:homepage <https://doi.org/10.1109/LES.2013.2278740>
dc:identifier DBLP journals/esl/YangMSP14 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FLES.2013.2278740 (xsd:string)
dcterms:issued 2014 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/esl>
rdfs:label Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dhiraj_K._Pradhan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jimson_Mathew>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rishad_A._Shafik>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yuanfan_Yang>
swrc:number 1 (xsd:string)
swrc:pages 12-15 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/esl/YangMSP14/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/esl/YangMSP14>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/esl/esl6.html#YangMSP14>
rdfs:seeAlso <https://doi.org/10.1109/LES.2013.2278740>
dc:title Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 6 (xsd:string)