A Historical Perspective on Hardware AI Inference, Charge-Based Computational Circuits and an 8 bit Charge-Based Multiply-Add Core in 16 nm FinFET CMOS. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Andreas_G._Andreou>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Kayode_A._Sanni>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FJETCAS.2019.2933795>
foaf:homepage	<https://doi.org/10.1109/JETCAS.2019.2933795>
dc:identifier	DBLP journals/esticas/SanniA19 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FJETCAS.2019.2933795 (xsd:string)
dcterms:issued	2019 (xsd:gYear)
swrc:journal	<https://dblp.l3s.de/d2r/resource/journals/esticas>
rdfs:label	A Historical Perspective on Hardware AI Inference, Charge-Based Computational Circuits and an 8 bit Charge-Based Multiply-Add Core in 16 nm FinFET CMOS. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Andreas_G._Andreou>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Kayode_A._Sanni>
swrc:number	3 (xsd:string)
swrc:pages	532-543 (xsd:string)
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/journals/esticas/esticas9.html#SanniA19>
rdfs:seeAlso	<https://doi.org/10.1109/JETCAS.2019.2933795>
dc:title	A Historical Perspective on Hardware AI Inference, Charge-Based Computational Circuits and an 8 bit Charge-Based Multiply-Add Core in 16 nm FinFET CMOS. (xsd:string)
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swrc:volume	9 (xsd:string)