A hierarchical test generation methodology for digital circuits. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Debashis_Bhattacharya>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/John_P._Hayes>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1007%2FBF00137388>
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dc:identifier	DBLP journals/et/BhattacharyaH90 (xsd:string)
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dcterms:issued	1990 (xsd:gYear)
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rdfs:label	A hierarchical test generation methodology for digital circuits. (xsd:string)
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swrc:number	2 (xsd:string)
swrc:pages	103-123 (xsd:string)
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rdfs:seeAlso	<https://doi.org/10.1007/BF00137388>
dc:subject	digital circuits; fault modeling; hierarchical testing; high-level circuit models; test generation (xsd:string)
dc:title	A hierarchical test generation methodology for digital circuits. (xsd:string)
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