A Gated Clock Scheme for Low Power Testing of Logic Cores.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/et/BonhommeGGLPV06
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2006
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A Gated Clock Scheme for Low Power Testing of Logic Cores.
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dc:
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low power design; low power test; test-per-scan; test-per-clock
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A Gated Clock Scheme for Low Power Testing of Logic Cores.
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