Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/et/BorriHDGPV05
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Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test.
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memory testing; dynamic faults; address decoders; core-cells
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Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test.
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