A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/et/ChangIR00
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/et/ChangIR00
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Elizabeth_M._Rudnick
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ta-Chung_Chang
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Vikram_Iyengar
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1023%2FA%3A1008311916502
>
foaf:
homepage
<
https://doi.org/10.1023/A:1008311916502
>
dc:
identifier
DBLP journals/et/ChangIR00
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1023%2FA%3A1008311916502
(xsd:string)
dcterms:
issued
2000
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/et
>
rdfs:
label
A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Elizabeth_M._Rudnick
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ta-Chung_Chang
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Vikram_Iyengar
>
swrc:
number
1-2
(xsd:string)
swrc:
pages
13-27
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/et/ChangIR00/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/et/ChangIR00
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/et/et16.html#ChangIR00
>
rdfs:
seeAlso
<
https://doi.org/10.1023/A:1008311916502
>
dc:
subject
architectural verification; biased random instruction generation; correctness checking; coverage metrics; design error coverage; design verification
(xsd:string)
dc:
title
A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
16
(xsd:string)