Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/et/DiL07
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2007
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Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems.
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2-3
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175-192
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dc:
subject
cellular arrays; delay-insensitive circuit; Reed-Muller expression; stuck-at fault; layout; nanoscale circuit
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dc:
title
Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems.
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