Error Detection Enhancement in PowerPC Architecture-based Embedded Processors.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/et/FazeliFM08
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DOI doi.org%2F10.1007%2Fs10836-007-5017-3
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dcterms:
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2008
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Error Detection Enhancement in PowerPC Architecture-based Embedded Processors.
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swrc:
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1-3
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swrc:
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21-33
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dc:
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Concurrent error detection; Control flow checking; Physical fault injection; Power supply disturbances
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title
Error Detection Enhancement in PowerPC Architecture-based Embedded Processors.
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24
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