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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/et/GarciaAMRH99>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Antonio_J._Acosta_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/J._M._Mora>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/J._Ramos>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_Luis_Huertas>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/T._A._Garc%E2%88%9A%E2%89%A0a>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1023%2FA%3A1008388318835>
foaf:homepage <https://doi.org/10.1023/A:1008388318835>
dc:identifier DBLP journals/et/GarciaAMRH99 (xsd:string)
dc:identifier DOI doi.org%2F10.1023%2FA%3A1008388318835 (xsd:string)
dcterms:issued 1999 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/et>
rdfs:label Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Antonio_J._Acosta_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/J._M._Mora>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/J._Ramos>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_Luis_Huertas>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/T._A._Garc%E2%88%9A%E2%89%A0a>
swrc:number 1-2 (xsd:string)
swrc:pages 115-127 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/et/GarciaAMRH99/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/et/GarciaAMRH99>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/et/et15.html#GarciaAMRH99>
rdfs:seeAlso <https://doi.org/10.1023/A:1008388318835>
dc:subject MCM testing; boundary-scan; self-timed CMOS design; testing interconnections (xsd:string)
dc:title Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 15 (xsd:string)