Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/et/GodambeS98
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1998
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Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS.
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dc:
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analog test; fault modeling; fault simulation; noise; jitter; behavioral fault modeling
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Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS.
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