Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/et/HamdiouiG00
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2000
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Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy.
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5
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487-498
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dc:
subject
multi-port memories; single-port memories; fault models; address decoder faults; march tests; fault coverage; read-only ports; write-only ports
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Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy.
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16
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