Designing "Dual Personality" IEEE 1149.1 Compliant Multi-Chip Modules.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/et/Jarwala97
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1997
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Designing "Dual Personality" IEEE 1149.1 Compliant Multi-Chip Modules.
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77-86
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boundary-scan; design-for-testability; module test
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Designing "Dual Personality" IEEE 1149.1 Compliant Multi-Chip Modules.
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