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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/et/JuniorRSTVT05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/D._Barros_J%E2%88%9A%C4%BCnior>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fabian_Vargas_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Isabel_C._Teixeira>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jo%E2%88%9A%C2%A3o_Paulo_Teixeira_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marcelino_B._Santos>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marcial_Jes%E2%88%9A%C4%BCs_Rodr%E2%88%9A%E2%89%A0guez-Irago>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs10836-005-0972-z>
foaf:homepage <https://doi.org/10.1007/s10836-005-0972-z>
dc:identifier DBLP journals/et/JuniorRSTVT05 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs10836-005-0972-z (xsd:string)
dcterms:issued 2005 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/et>
rdfs:label Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/D._Barros_J%E2%88%9A%C4%BCnior>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fabian_Vargas_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Isabel_C._Teixeira>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jo%E2%88%9A%C2%A3o_Paulo_Teixeira_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marcelino_B._Santos>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marcial_Jes%E2%88%9A%C4%BCs_Rodr%E2%88%9A%E2%89%A0guez-Irago>
swrc:number 4 (xsd:string)
swrc:pages 349-363 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/et/JuniorRSTVT05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/et/JuniorRSTVT05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/et/et21.html#JuniorRSTVT05>
rdfs:seeAlso <https://doi.org/10.1007/s10836-005-0972-z>
dc:subject fault tolerance; intermittent faults modeling and simulation; digital SoC; EMI/EMC standard compliance; delay fault simulation; power supply voltage transients (xsd:string)
dc:title Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 21 (xsd:string)